By Francisco Serra-Graells
Low-Voltage CMOS Log Companding Analog layout provides in element state of the art analog circuit concepts for the very low-voltage and low-power layout of systems-on-chip in CMOS applied sciences. The proposed method is especially according to bases: the instant Log Companding conception, and the MOSFET working within the subthreshold area. the previous permits internal compression of the voltage dynamic-range for terribly low-voltage operation, whereas the latter is suitable with CMOS applied sciences and compatible for low-power circuits. the necessary historical past at the particular modeling of the MOS transistor for Companding is equipped at first. Following this basic process, a whole set of CMOS simple development blocks is proposed and analyzed for a wide selection of analog sign processing. particularly, the lined components comprise: amplification and AGC, arbitrary filtering, PTAT new release, and pulse period modulation (PDM). for every subject, numerous case reports are thought of to illustrate the layout technique. additionally, built-in examples in 1.2um and 0.35um CMOS applied sciences are mentioned to ensure the nice contract among layout equations and experimental information. The ensuing analog circuit topologies convey very low-voltage (i.e. 1V) and low-power (few tenths of uA) services. except those particular layout examples, a true business software within the box of listening to aids can be awarded because the major demonstrator of the entire proposed simple construction blocks. This system-on-chip indicates precise 1V operation, excessive flexibility via electronic programmability and intensely low-power intake (about 300uA together with the Class-D amplifier). As a outcome, the pronounced ASIC can meet the standards of an entire kin of universal listening to reduction types. In end, this booklet is addressed to either ASIC designers who can practice its contents to the synthesis of very low-power systems-on-chip in average CMOS applied sciences, in addition to to the academics of contemporary circuit layout in digital engineering.