By G.E. Taylor, G. Russell
This publication covers algorithms and purposes of recommendations from the bogus intelligence neighborhood in CAD for VLSI.
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Extra info for Algorithmic and knowledge based CAD for VLSI
The problem in hardware synthesis is to take an initial specification, frequently in the form of boolean equations or register transfer statements, and map these efficiently into silicon. Such languages do not lend themselves very well to formal reasoning, and recent research efforts have only concentrated on mapping formal languages into silicon. The use of formal languages makes it difficult to generate an efficient layout, since a much larger design space needs to be explored than when low level languages are used.
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